The cache memory market is growing at a rapid pace with the advent of the high-performance 32-bit microprocessors. The cache memory is a small but fast memory block typically inserted between the CPU and the primary memory. The CPU fetches data and instructions from the cache when it is determined that the desired data and instructions reside in the cache. Since the cache memory is about ten times faster than the primary memory, the CPU-memory speed gap is considerably reduced when accessing the cache.
In the cache memory scheme, the primary memory and the cache memory are usually divided into equal-size pages. Required pages from the primary memory are first transferred into the cache and execution of the program begins with the CPU fetching data and instructions from the cache. If the address of the instruction to be executed or the data to be fetched is not in the cache memory (i.e., a miss), an appropriate page from the primary memory is transferred into the cache memory. If the address is in the cache memory (i.e., a hit), the execution of instructions from the cache continues. One method for writing data into a primary memory location using a cache scheme requires a tag to be associated with each cache page. The tag indicates whether a page is altered or not due to a memory Write operation. If not altered, the page is discarded and another required page is brought into the cache. Some type of virtual memory management scheme is required to manage the cache-primary memory instructions.
Since the cache memory compares each address generated by the microprocessor with the tag to determine if there is a hit, it is important that the integrity of this tag be maintained such that an invalid hit does not occur. An invalid hit can occur, for example, upon power up of the system since a random sequence of bits is initially stored in the tag. To determine the validity of the tags, one bit in each of the tags is designated as a valid bit. The I/O associated with this valid bit is typically tied to a positive voltage representing the logic high voltage which, when written to the valid bit, provides an indication of a valid tag. Initially, the entire memory is flash cleared such that all zeroes are stored in each of the tag bits until a tag is stored in the address cache, at which time the logic "1" is written in the valid bit for the tag written to. By determining whether the valid bit for the addressed tag is a logic "1", the presence of a hit can be determined.
In prior systems, the memory utilized for both the address cache and the data cache in the cache system utilized static random access memories (SRAM's). The entire memory was cleared upon power up of the system by storing a zero in each of the memory locations by various methods. One method required sequentially addressing all of the memory locations and forcing a zero therein. Another system forces all of the memory locations to zero. One disadvantage to this latter system is that drivers must be present which can drive all of the memory locations to a "0" logic state. In addition, some type of interconnection is required for each of the memory cells which increases the amount of space occupied by the memory array. Typically, each column of memory cells will require a separate run of conductive material to interface with each of the memory cells for the clear function. The drive requirements for clearing all of the memory cells results in relatively large drive transistors. In any event, it is not necessary to clear the entire memory since only one bit determines whether there is valid tag information in a cache memory. There therefore exists a need for a more versatile memory that allows clearing of less than all of the memory cells.